Semiconductor device outputting reference voltages

ABSTRACT

Power consumption of a signal processing circuit is reduced. Further, power consumption of a semiconductor device including the signal processing circuit is reduced. The signal processing circuit includes a reference voltage generation circuit, a voltage divider circuit, an operational amplifier, a bias circuit for supplying bias current to the operational amplifier, and first and second holding circuits. The first holding circuit is connected between the reference voltage generation circuit and the bias circuit. The second holding circuit is connected between the voltage divider circuit and a non-inverting input terminal of the operational amplifier. Reference voltage from the reference voltage generation circuit and reference voltage from the voltage divider circuit can be held in the first and second holding circuits, respectively, so that the reference voltage generation circuit can stop operating. Thus, power consumption of the reference voltage generation circuit can be reduced.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device in which supply of power supply voltage to a signal processing circuit can be stopped. In this specification and the like, a semiconductor device refers to all types of devices which can function by utilizing semiconductor characteristics; an electro-optical device, a light-emitting display device, a semiconductor circuit, and an electronic device are all semiconductor devices.

2. Description of the Related Art

In recent years, a reduction in power consumption of an electronic device in operation has been highly required. In order to reduce power consumption of an electronic device, operation of each logic circuit is controlled in accordance with operation of a signal processing circuit.

In a voltage regulator, which is an example of a signal processing circuit, a three-stage structure operation with a high power supply rejection ratio and favorable transient response characteristics and a two-stage structure operation with low current consumption are automatically switched (see Patent Document 1). The three-stage structure includes a first differential amplifier circuit, a second differential amplifier circuit, and an output transistor, and the second-stage structure includes the second differential amplifier circuit and the output transistor.

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.     2011-096210

SUMMARY OF THE INVENTION

However, in the voltage regulator disclosed in Patent Document 1, even in operation with very small current, a reference voltage generation circuit consumes power as long as current is supplied from a power supply to the reference voltage generation circuit. Therefore, it cannot be said that power consumption of the signal processing circuit is sufficiently reduced.

In view of the above problem, an object of an embodiment of the present invention is to reduce power consumption of a signal processing circuit. Further, it is an object to reduce power consumption of a semiconductor device including the signal processing circuit.

A semiconductor device according to an embodiment of the present invention includes a reference voltage generation circuit, a voltage divider circuit, an operational amplifier, a bias circuit for supplying bias current to the operational amplifier, a first holding circuit, and a second holding circuit. The first holding circuit is connected between the reference voltage generation circuit and the bias circuit. The second holding circuit is connected between the voltage divider circuit and a non-inverting input terminal of the operational amplifier.

The first and second holding circuits each include a switch and a capacitor. One end of the switch of the first holding circuit is connected to the reference voltage generation circuit, and the other end of the switch of the first holding circuit is connected to the bias circuit and one of a pair of electrodes of the capacitor of the first holding circuit. One end of the switch of the second holding circuit is connected to the voltage divider circuit, and the other end of the switch of the second holding circuit is connected to the operational amplifier and one of a pair of electrodes of the capacitor of the second holding circuit. A transistor with significantly small off-state current is used as each of the switches.

As the transistor with extremely small off-state current, a transistor whose channel is formed in a film or a substrate including a semiconductor having a wider band gap than silicon can be used. As a semiconductor having a wider band gap than silicon, a compound semiconductor such as an oxide semiconductor or a nitride semiconductor is given. For example, a transistor having a channel in an oxide semiconductor film can be used as the transistor with significantly small off-state current.

Note that in this specification and the like, off-state current is current that flows between a source and a drain when a transistor is in an off state. In an n-channel transistor (e.g., with a threshold voltage of about 0 V to 2 V), the off-state current means current that flows between a source and a drain when negative voltage is applied between a gate and the source.

When a transistor whose channel is formed in an oxide semiconductor film is used as a switch, even in the case where a potential of a node to which the switch and a capacitor are connected is kept constant and then the switch is turned off, the amount of electric charges leaking through the switch can be extremely small.

Therefore, by turning off the switch included in the first holding circuit, voltage output from the reference voltage generation circuit can be held in a node to which the switch and the capacitor of the first holding circuit are connected. Further, by turning off the switch included in the second holding circuit, voltage output from the voltage divider circuit can be held in a node to which the switch and the capacitor of the second holding circuit are connected.

Accordingly, the reference voltage generation circuit does not need to keep outputting voltage to the bias circuit or the operational amplifier, so that the reference voltage generation circuit does not need to continuously operate. Thus, supply of power to the reference voltage generation circuit can be stopped, whereby power consumed by the reference voltage generation circuit can be reduced.

A semiconductor device according to an embodiment of the present invention includes a reference voltage generation circuit which is connected between a first terminal supplied with first power supply voltage and a second terminal supplied with second power supply voltage and outputs first reference voltage and second reference voltage; a voltage divider circuit which is connected between the first terminal and the second terminal and divides the second reference voltage to output reference voltage; a first switch which is connected between the first terminal and the reference voltage generation circuit and is turned on or off in accordance with a first signal; an operational amplifier whose non-inverting input terminal is supplied with the reference voltage from the voltage divider circuit and whose inverting input terminal is supplied with output voltage; a bias circuit which supplies bias current to the operational amplifier; a first holding circuit which is connected between the reference voltage generation circuit and the bias circuit and holds the first reference voltage in accordance with a second signal; and a second holding circuit which is connected between the voltage divider circuit and the non-inverting input terminal of the operational amplifier and holds the reference voltage output from the voltage divider circuit in accordance with the second signal.

A semiconductor device according to an embodiment of the present invention includes a reference voltage generation circuit which is connected between a first terminal supplied with first power supply voltage and a second terminal supplied with second power supply voltage and outputs first reference voltage and second reference voltage; a voltage divider circuit which is connected between the first terminal and the second terminal and divides the second reference voltage to output reference voltage; a first switch which is connected between the first terminal and the reference voltage generation circuit and is turned on or off in accordance with a first signal; an operational amplifier whose non-inverting input terminal is supplied with the reference voltage from the voltage divider circuit and whose inverting input terminal is supplied with output voltage; a bias circuit which is connected between the operational amplifier and the second terminal and supplies bias current to the operational amplifier; a first holding circuit which is connected between the reference voltage generation circuit and the bias circuit and holds the first reference voltage in accordance with a second signal; and a second holding circuit which is connected between the voltage divider circuit and the non-inverting input terminal of the operational amplifier and holds the reference voltage output from the voltage divider circuit in accordance with the second signal.

A semiconductor device according to an embodiment of the present invention includes a reference voltage generation circuit which is connected between a first terminal supplied with first power supply voltage and a second terminal supplied with second power supply voltage and outputs reference voltage; a voltage divider circuit which is connected between the first terminal and the second terminal and divides the reference voltage output from the reference voltage generation circuit to output reference voltage; a first switch which is connected between the first terminal and the reference voltage generation circuit and is turned on or off in accordance with a first signal; an operational amplifier whose non-inverting input terminal is supplied with the reference voltage from the voltage divider circuit and whose inverting input terminal is supplied with output voltage; a bias circuit which is connected between the operational amplifier and the first terminal and supplies bias current to the operational amplifier; a first holding circuit which is connected between the reference voltage generation circuit and the bias circuit and holds the reference voltage output from the reference voltage generation circuit in accordance with a second signal; and a second holding circuit which is connected between the voltage divider circuit and the non-inverting input terminal of the operational amplifier and holds the reference voltage output from the voltage divider circuit in accordance with the second signal.

In each of the semiconductor devices, the first and second holding circuits each include a second switch and a capacitor. The second switch is turned on or off in accordance with the second signal. The second switch is a transistor whose channel is formed in an oxide semiconductor.

A semiconductor device according to an embodiment of the present invention includes a reference voltage generation circuit which is connected between a first terminal supplied with first power supply voltage and a second terminal supplied with second power supply voltage and outputs first reference voltage and second reference voltage; a first switch which is connected between the first terminal and the reference voltage generation circuit and is turned on or off in accordance with a first signal; a voltage divider circuit which is connected between the first terminal and the second terminal and divides the second reference voltage to output reference voltage; an operational amplifier whose non-inverting input terminal is supplied with the reference voltage from the voltage divider circuit and whose inverting input terminal is supplied with output voltage; a first bias circuit which is connected between the operational amplifier and the first terminal and supplies bias current to the operational amplifier; a second bias circuit which is connected between the operational amplifier and the second terminal and supplies bias current to the operational amplifier; a first holding circuit which is connected between the reference voltage generation circuit and the first bias circuit and holds the first reference voltage in accordance with a second signal; a second holding circuit which is connected between the reference voltage generation circuit and the second bias circuit and holds the second reference voltage in accordance with the second signal; and a third holding circuit which is connected between the voltage divider circuit and the non-inverting input terminal of the operational amplifier and holds the reference voltage output from the voltage divider circuit in accordance with the second signal.

In the above semiconductor device, the first to third holding circuits each include a second switch and a capacitor. The second switch is turned on or off in accordance with the second signal. The second switch is a transistor whose channel is formed in an oxide semiconductor.

In each of the semiconductor devices, a channel of the first switch is formed in an oxide semiconductor.

Note that the oxide semiconductor used for the transistors is preferably a purified oxide semiconductor in which impurities serving as electron donors (donors), such as moisture or hydrogen, are reduced and oxygen vacancies are reduced. The purified oxide semiconductor is an i-type (intrinsic) semiconductor or a substantially i-type semiconductor. Therefore, a transistor including the oxide semiconductor has a characteristic of significantly small off-state current. Furthermore, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. With the use of the oxide semiconductor film which is purified by sufficiently reducing the concentration of impurities such as moisture or hydrogen and by reducing oxygen vacancies, the off-state current of the transistor can be significantly reduced.

Specifically, various experiments can prove small off-state current of a transistor in which a purified oxide semiconductor is used for a semiconductor film. For example, even in an element with a channel width of 1×10⁶ μm and a channel length of 10 μm, in a range from 1 V to 10 V of voltage (drain voltage) between a source terminal and a drain terminal, off-state current can be smaller than or equal to the measurement limit of a semiconductor parameter analyzer, that is, smaller than or equal to 1×10⁻¹³ A. In this case, it can be found that an off-state current density corresponding to a value obtained by dividing the off-state current by the channel width of the transistor is less than or equal to 100 zA/μm. In addition, a capacitor and a transistor were connected to each other and an off-state current density was measured by using a circuit in which electric charge flowing into or from the capacitor was controlled by the transistor. In the measurement, the purified oxide semiconductor film was used for a channel formation region in the transistor, and the off-state current density of the transistor was measured from change in the amount of electric charge of the capacitor per unit time. As a result, it is found that, in the case where the voltage between the source terminal and the drain terminal of the transistor is 3 V, a smaller off-state current density of several tens of yoctoamperes per micrometer (yA/μm) can be obtained. Consequently, it can be said that a transistor whose channel formation region is formed in a purified oxide semiconductor film has much smaller off-state current than a transistor including silicon.

Thus, according to an embodiment of the present invention, power consumption of a signal processing circuit can be sufficiently reduced. Further, power consumption of a semiconductor device including the signal processing circuit can be sufficiently reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a block diagram of a signal processing circuit;

FIG. 2 is a block diagram of a signal processing circuit;

FIG. 3 is a circuit diagram of a signal processing circuit;

FIG. 4 is a block diagram of a signal processing circuit;

FIG. 5 is a block diagram of a signal processing circuit;

FIG. 6 is a circuit diagram of a signal processing circuit;

FIG. 7 is a block diagram of a signal processing circuit;

FIG. 8 is a circuit diagram illustrating part of a signal processing circuit;

FIG. 9 is a block diagram of a power supply control device;

FIG. 10 is a cross-sectional view illustrating a method for manufacturing transistors; and

FIG. 11 is a circuit diagram of a signal processing circuit.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the scope and spirit of the present invention. Accordingly, the present invention should not be construed as being limited to the description of the embodiments below.

Embodiment 1

In this embodiment, a signal processing circuit according to an embodiment of the present invention will be described with reference to FIG. 1, FIG. 2, and FIG. 3.

FIG. 1 is a block diagram of a signal processing circuit. The signal processing circuit illustrated in FIG. 1 includes a reference voltage generation circuit 101, a voltage divider circuit 102, a switch 103, an operational amplifier 104, a bias circuit 105, a holding circuit 106, and a holding circuit 107.

The reference voltage generation circuit 101 is connected between a first terminal supplied with first power supply voltage V1 and a second terminal supplied with second power supply voltage V2, and outputs reference voltage Va to the bias circuit 105 and reference voltage Vb to the voltage divider circuit 102. The first power supply voltage V1 is VDD and the second power supply voltage V2 is GND, for example.

The voltage divider circuit 102 is connected between the first terminal and the second terminal, and divides the reference voltage Vb to output reference voltage Vref to a non-inverting input terminal of the operational amplifier 104.

The switch 103 is connected between the first terminal and the reference voltage generation circuit 101, and is turned on or off in accordance with a control signal SEL1. In the case where the switch 103 is in an on state, the first power supply voltage V1 is supplied to the reference voltage generation circuit 101 from the first terminal. In the case where the switch 103 is in an off state, supply of the first power supply voltage V1 to the reference voltage generation circuit 101 from the first terminal is stopped.

In the operational amplifier 104, the reference voltage Vref is input to the non-inverting input terminal and output voltage Vout is output from an output terminal. Further, part of the output voltage Vout is fed back to an inverting input terminal.

The bias circuit 105 is connected between the second terminal and the operational amplifier 104 and supplies bias current to the operational amplifier 104.

The holding circuit 106 is connected between the reference voltage generation circuit 101 and the bias circuit 105. The holding circuit 106 includes a switch 111 and a capacitor 112. One end of the switch 111 is connected to the reference voltage generation circuit 101 and the other end is connected to the bias circuit 105 and one of a pair of electrodes of the capacitor 112. The other of the pair of electrodes of the capacitor 112 is connected to the second terminal. Here, a connection point to which the other end of the switch 111, the one of the pair of electrodes of the capacitor 112, and the bias circuit 105 are connected is a node A.

The switch 111 is turned on or off in accordance with a control signal SEL2. In the case where the switch 111 is in an on state, the reference voltage Va output from the reference voltage generation circuit 101 is supplied to the bias circuit 105. In the case where the switch 111 is in an off state, the reference voltage Va output from the reference voltage generation circuit 101 is held in the node A.

The holding circuit 107 is connected between the voltage divider circuit 102 and the non-inverting input terminal of the operational amplifier 104. The holding circuit 107 includes a switch 113 and a capacitor 114. One end of the switch 113 is connected to the voltage divider circuit 102 and the other end is connected to one of a pair of electrodes of the capacitor 114 and the non-inverting input terminal of the operational amplifier 104. The other of the pair of electrodes of the capacitor 114 is connected to the second terminal. Here, a connection point to which the other end of the switch 113, the one of the pair of electrodes of the capacitor 114, and the non-inverting input terminal of the operational amplifier 104 are connected is a node B.

The switch 113 is turned on or off in accordance with the control signal SEL2. In the case where the switch 113 is in an on state, the reference voltage Vref output from the voltage divider circuit 102 is supplied to the non-inverting input terminal of the operational amplifier 104. In the case where the switch 113 is in an off state, the reference voltage Vref output from the voltage divider circuit 102 is held in the node B.

FIG. 2 illustrates examples of the switch 103, the bias circuit 105, the holding circuit 106, and the holding circuit 107 in the signal processing circuit illustrated in FIG. 1.

As the switch 103, for example, a transistor 115 which is turned on or off in accordance with the control signal SEL1 is used.

As the bias circuit 105, for example, a transistor 116 which is turned on or off in accordance with the reference voltage Va output from the reference voltage generation circuit 101 is used. The transistor 116 is turned on when voltage in the node A is higher than or equal to the threshold voltage of the transistor 116. In this case, the bias current is supplied to the operational amplifier 104. The transistor 116 is turned off when the voltage in the node A is lower than the threshold voltage of the transistor 116. In this case, supply of the bias current to the operational amplifier 104 is stopped. Note that the transistor 116 is an n-channel transistor in FIG. 2.

The switch 111 in the holding circuit 106 is, for example, a transistor 117 which is turned on or off in accordance with the control signal SEL2. Here, a transistor with significantly small off-state current is used as the transistor 117.

The switch 113 in the holding circuit 107 is, for example, a transistor 118 which is turned on or off in accordance with the control signal SEL2. Here, a transistor with significantly small off-state current is used as the transistor 118.

As the transistor with significantly small off-state current, a transistor whose channel is formed in a film or a substrate including a semiconductor having a wider band gap than silicon can be used. As a semiconductor having a wider band gap than silicon, a compound semiconductor such as an oxide semiconductor or a nitride semiconductor is given, for example. For example, a transistor having a channel in an oxide semiconductor film can be used as the transistor with extremely small off-state current.

When the transistor 117 with extremely small off-state current is used as the switch 111 in the holding circuit 106 and the transistor 117 is in an off state, voltage of the one of the pair of electrodes of the capacitor 112 can be held for a long time. In other words, in the case where the switch 111 is in an off state, the voltage of the node A in the holding circuit 106 can be held for a long time.

When the transistor 118 with significantly small off-state current is used as the switch 113 in the holding circuit 107 and the transistor 118 is in an off state, voltage of the one of the pair of electrodes of the capacitor 114 can be held for a long time. In other words, in the case where the switch 113 is in an off state, the voltage of the node B in the holding circuit 107 can be held for a long time.

Next, operation of the signal processing circuit illustrated in FIG. 2 is described.

First, the control signal SEL1 is input to the transistor 115 and the transistor 115 is turned on, whereby the first power supply voltage V1 is supplied to the reference voltage generation circuit 101 from the first terminal. In the case where the transistor 115 is an n-channel transistor, a high-level potential may be input as the control signal SEL1, whereas in the case where the transistor 115 is a p-channel transistor, a low-level potential may be input as the control signal SEL1. Note that described below is the case where the transistor 115, the transistor 117, and the transistor 118 are n-channel transistors. The reference voltage generation circuit 101 operates with the first power supply voltage V1 supplied thereto, and outputs the reference voltage Vb to the voltage divider circuit 102 and the reference voltage Va to the holding circuit 106.

The voltage divider circuit 102 outputs the reference voltage Vref obtained by dividing the reference voltage Vb to the holding circuit 107.

The control signal SEL2 is set to a high level and the transistor 117 and the transistor 118 are turned on. When the transistor 117 is turned on, the reference voltage Va output from the reference voltage generation circuit 101 is supplied to the transistor 116. Thus, the transistor 116 is turned on and the second power supply voltage V2 is supplied to the operational amplifier 104 from the second terminal. Further, when the transistor 118 is turned on, the reference voltage Vref output from the voltage divider circuit 102 is output to the non-inverting input terminal of the operational amplifier 104. Thus, the operational amplifier 104 operates: the output voltage Vout is output from the output terminal and part of the output voltage Vout is output to the inverting input terminal of the operational amplifier 104.

After the signal processing circuit illustrated in FIG. 2 reaches a steady state (the state where the reference voltage Va is normally supplied to the bias circuit 105 and the reference voltage Vref is normally supplied to the non-inverting input terminal of the operational amplifier 104), the control signal SEL2 is set to a low level, and thus, the transistor 117 and the transistor 118 are turned off. Since the transistor 117 and the transistor 118 are transistors with significantly small off-state current, the voltage in the node A (reference voltage Va) and the voltage in the node B (reference voltage Vref) can be held for a long time.

Next, the control signal SEL1 is set to a low level and the transistor 115 is turned off. Thus, supply of the first power supply voltage V1 to the reference voltage generation circuit 101 from the first terminal is stopped. Since the first power supply voltage V1 is not supplied to the reference voltage generation circuit 101, the reference voltage generation circuit 101 stops operating.

In the signal processing circuit illustrated in FIG. 2, the transistor 117 with significantly small off-state current is used in the holding circuit 106. Therefore, by turning off the transistor 117, the voltage in the node A (reference voltage Va) can be held for a long time. Thus, even when the reference voltage generation circuit 101 stops operating, the reference voltage Va can still be supplied to the transistor 116. Similarly, the transistor 118 with significantly small off-state current is used in the holding circuit 107. Therefore, by turning off the transistor 118, the voltage in the node B (reference voltage Vref) can be held for a long time. Thus, even when the reference voltage generation circuit 101 stops operating, the reference voltage Vref can still be supplied to the non-inverting input terminal of the operational amplifier 104.

For example, in the case where a transistor including silicon is used as the switch 111, the off-state current thereof is 1 pA. In the case where the capacitance of the capacitor 112 is, for example, 1 pF, the node A holds the reference voltage Va with a change less than 1 mV for only 1 millisecond. Accordingly, when the reference voltage generation circuit 101 stops operating, the bias circuit 105 also stops operating. Therefore, the reference voltage generation circuit 101 cannot stop operating even when the signal processing circuit reaches a steady state.

However, according to an embodiment of the present invention, since the transistor 117 including an oxide semiconductor is used as the switch 111, the off-state current thereof can be 100 yA. When the capacitance of the capacitor 112 is, for example, 1 pF, the node A can hold the reference voltage Va with a change less than 1 mV for 10⁷ seconds (approximately 115 days).

Similarly, since the transistor 118 including an oxide semiconductor is used as the switch 113, the off-state current thereof can be 100 yA. When the capacitance of the capacitor 114 is, for example, 1 pF, the node B can hold the reference voltage Vref with a change less than 1 mV for 10⁷ seconds (approximately 115 days).

Accordingly, the reference voltage generation circuit 101 can stop operating for 10⁷ seconds (approximately 115 days). Before 10⁷ seconds (approximately 115 days) pass, the reference voltage generation circuit 101 may operate and the reference voltage Va and the reference voltage Vref may be output to the holding circuit 106 and the holding circuit 107, respectively, by turning on the switch 103 and supplying the first power supply voltage V1 to the reference voltage generation circuit 101.

In a conventional reference voltage generation circuit, power supply voltage needs to be always supplied while the reference voltage generation circuit outputs voltage. Therefore, power is always consumed by the conventional reference voltage generation circuit.

In contrast, in an embodiment of the present invention, transistors each of whose channels is formed in an oxide semiconductor film are used as the switches 111 and 113. For example, even when the switch 113 is turned off after a potential of the node B to which the switch 113 and the capacitor 114 are connected is kept constant, the amount of electric charges leaking through the switch 113 can be extremely small.

Therefore, when the switch 111 included in the holding circuit 106 is in an off state, the voltage output from the reference voltage generation circuit 101 can be held in the node A to which the switch 111 and the capacitor 112 are connected. Further, when the switch 113 included in the holding circuit 107 is in an off state, the voltage output from the voltage divider circuit 102 can be held in the node B to which the switch 113 and the capacitor 114 are connected.

Accordingly, the reference voltage generation circuit 101 does not need to keep outputting voltage to the bias circuit 105 or the operational amplifier 104, so that the reference voltage generation circuit 101 does not need to continuously operate. Thus, supply of power to the reference voltage generation circuit 101 can be stopped by turning off the switch 103, whereby power consumed by the reference voltage generation circuit 101 can be reduced.

In this embodiment, although the case where the switch 111 and the switch 113 are each a transistor including an oxide semiconductor is described, the switch 103 may be a transistor including an oxide semiconductor.

Further, the switch 103, the switch 111, and the switch 113 may each be a transistor in which upper and lower gates are provided with an oxide semiconductor layer provided therebetween. In the case of the switch 103, the control signal SEL1 can be input to one gate, and a different control signal can be input to the other gate. In the case of the switch 111 and the switch 113, the control signal SEL2 can be input to one gate, and a different control signal can be input to the other gate. The different control signal may be a signal with a fixed potential. The fixed potential may be either a low power supply potential or a high power supply potential. Note that the upper and lower gates may be electrically connected to each other and a control signal may be input. The threshold voltage of the transistor or the like can be controlled by a signal input to the other gate. Further, the off-state current of the transistor can be further reduced.

Although the case where the control signal SEL1 and the control signal SEL2 are different signals is described in this embodiment, the control signal SEL1 and the control signal SEL2 may be the same signal.

In the case where the reference voltage generation circuit 101, the voltage divider circuit 102, and the operational amplifier 104 include transistors, the transistors may each be a transistor whose channel is formed in a layer or a substrate including a semiconductor other than an oxide semiconductor. For example, the transistors can each be a transistor whose channel is formed in a silicon layer or a silicon substrate.

FIG. 3 illustrates the signal processing circuit illustrated in FIG. 1 in more detail.

The reference voltage generation circuit 101 includes transistors 131 to 134 and a resistor 135. The transistors 131 and 132 are p-channel transistors, and the transistors 133 and 134 are n-channel transistors. A node a is connected to one of a source and a drain of the transistor 115 in the holding circuit 106, and a node b is connected to a gate of a transistor 136 in the voltage divider circuit 102. The reference voltage Va is voltage in the node a and the reference voltage Vb is voltage in the node b.

The voltage divider circuit 102 includes the transistor 136 and a resistor 137. The transistor 136 is a p-channel transistor. One of a source and a drain of the transistor 136 is connected to one of a source and a drain of the transistor 118 in the holding circuit 107.

The operational amplifier 104 includes transistors 138 to 141, a transistor 143, and a capacitor 144. The transistor 138, the transistor 139, and the transistor 143 are p-channel transistors, and the transistor 138 and the transistor 139 form a current mirror circuit. The transistor 140 and the transistor 141 are n-channel transistors and form a differential circuit. The transistor 143 and the capacitor 144 form a buffer circuit.

Although an example in which a signal processing circuit includes an operational amplifier is described in this embodiment, the signal processing circuit may include a comparator instead of the operational amplifier.

The bias circuit 105 includes the transistor 116 and a transistor 142. The transistor 116 and the transistor 142 are n-channel transistors.

In the signal processing circuit described in this embodiment, the holding circuit 106 is connected between the reference voltage generation circuit 101 and the bias circuit 105, so that the reference voltage Va output from the reference voltage generation circuit 101 can be held in the holding circuit 106. Further, the holding circuit 107 is connected between the voltage divider circuit 102 and the operational amplifier 104, so that the reference voltage Vref output from the voltage divider circuit 102 can be held in the holding circuit 107. Thus, the reference voltage generation circuit 101 can stop operating during a period in which the reference voltage Va is held in the holding circuit 106 and the reference voltage Vref is held in the holding circuit 107, so that power consumed by the reference voltage generation circuit 101 can be reduced. Consequently, power consumed by the signal processing circuit can be reduced.

The signal processing circuit described in this embodiment can be used for, for example, an AC-DC converter, a sensor, or the like. The signal processing circuit described in this embodiment is particularly effectively used in a circuit in which an analog circuit such as an operational amplifier or a comparator is used and a fixed voltage or a signal is continuously output.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 2

In this embodiment, another embodiment of a signal processing circuit according to an embodiment of the present invention will be described with reference to FIG. 4, FIG. 5, and FIG. 6.

FIG. 4 is a block diagram of a signal processing circuit. The signal processing circuit illustrated in FIG. 4 includes the reference voltage generation circuit 101, the voltage divider circuit 102, the switch 103, the operational amplifier 104, the holding circuit 107, a bias circuit 109, and a holding circuit 108.

The reference voltage generation circuit 101 is connected between the first terminal supplied with the first power supply voltage V1 and the second terminal supplied with the second power supply voltage V2, and outputs the reference voltage Vb to the bias circuit 109 and the voltage divider circuit 102. The first power supply voltage V1 is VDD and the second power supply voltage V2 is GND, for example.

The voltage divider circuit 102 is connected between the first terminal and the second terminal, and divides the reference voltage Vb to output the reference voltage Vref to the non-inverting input terminal of the operational amplifier 104.

The switch 103 is connected between the first terminal and the reference voltage generation circuit 101, and is turned on or off in accordance with the control signal SEL1. In the case where the switch 103 is in an on state, the first power supply voltage V1 is supplied to the reference voltage generation circuit 101 from the first terminal. In the case where the switch 103 is in an off state, supply of the first power supply voltage V1 to the reference voltage generation circuit 101 from the first terminal is stopped.

In the operational amplifier 104, the reference voltage Vref is input to the non-inverting input terminal and the output voltage Vout is output from the output terminal. Further, part of the output voltage Vout is fed back to the inverting input terminal.

The bias circuit 109 is connected between the first terminal and the operational amplifier 104 and supplies bias current to the operational amplifier 104.

The holding circuit 108 is connected between the reference voltage generation circuit 101 and the bias circuit 109. The holding circuit 108 includes a switch 119 and a capacitor 120. One end of the switch 119 is connected to the reference voltage generation circuit 101 and the other end is connected to the bias circuit 109 and one of a pair of electrodes of the capacitor 120. The other of the pair of electrodes of the capacitor 120 is connected to the first terminal. Here, a connection point to which the other end of the switch 119, the one of the pair of electrodes of the capacitor 120, and the bias circuit 109 are connected is a node C.

The switch 119 is turned on or off in accordance with the control signal SEL2. In the case where the switch 119 is in an on state, the reference voltage Vb output from the reference voltage generation circuit 101 is supplied to the bias circuit 109. In the case where the switch 119 is in an off state, the reference voltage Vb output from the reference voltage generation circuit 101 is held in the node C.

Since the structure of the holding circuit 107 is similar to that in Embodiment 1, detailed description thereof is omitted.

FIG. 5 illustrates examples of the bias circuit 109 and the holding circuit 108 in the signal processing circuit illustrated in FIG. 4.

As the bias circuit 109, for example, a transistor 121 which is turned on or off in accordance with the reference voltage Vb output from the reference voltage generation circuit 101 is used. The transistor 121 is turned on when voltage in the node C is higher than or equal to the threshold voltage of the transistor 121. In this case, the bias current is supplied to the operational amplifier 104. The transistor 121 is turned off when the voltage in the node C is lower than the threshold voltage of the transistor 121. In this case, supply of the bias current to the operational amplifier 104 is stopped. Note that the transistor 121 is a p-channel transistor in FIG. 5.

The switch 119 in the holding circuit 108 is, for example, a transistor 122 which is turned on or off in accordance with the control signal SEL2. Here, a transistor with significantly small off-state current is used as the transistor 122. Note that a transistor similar to the transistor 118 illustrated in FIG. 2 can be used as the transistor with significantly small off-state current.

When the transistor 122 with extremely small off-state current is used as the switch 119 in the holding circuit 108 and the transistor 122 is in an off state, voltage of the one of the pair of electrodes of the capacitor 120 can be held for a long time. In other words, in the case where the switch 119 is in an off state, the voltage in the node C in the holding circuit 108 can be held for a long time.

Next, operation of the signal processing circuit illustrated in FIG. 5 is described.

First, the control signal SEL1 is input to the transistor 115 and the transistor 115 is turned on, whereby the first power supply voltage V1 is supplied to the reference voltage generation circuit 101 from the first terminal. In the case where the transistor 115 is an n-channel transistor, a high-level potential may be input as the control signal SEL1, whereas in the case where the transistor 115 is a p-channel transistor, a low-level potential may be input as the control signal SEL1. Note that described below is the case where the transistor 115, the transistor 118, and the transistor 122 are n-channel transistors. The reference voltage generation circuit 101 operates with the first power supply voltage V1 supplied thereto, and outputs the reference voltage Vb to the holding circuit 108 and to the voltage divider circuit 102.

The voltage divider circuit 102 outputs the reference voltage Vref obtained by dividing the reference voltage Vb to the holding circuit 107.

The control signal SEL2 is set to a high level and the transistor 118 and the transistor 122 are turned on. When the transistor 122 is turned on, the reference voltage Vb output from the reference voltage generation circuit 101 is supplied to the transistor 121. Thus, the transistor 121 is turned on and the first power supply voltage V1 is supplied to the operational amplifier 104 from the first terminal. Further, when the transistor 118 is turned on, the reference voltage Vref output from the voltage divider circuit 102 is output to the non-inverting input terminal of the operational amplifier 104. Thus, the operational amplifier 104 operates: the output voltage Vout is output from the output terminal and part of the output voltage Vout is output to the inverting input terminal of the operational amplifier 104.

After the signal processing circuit illustrated in FIG. 5 reaches a steady state (the state where the reference voltage Vb is normally supplied to the transistor 121 and the reference voltage Vref is normally supplied to the non-inverting input terminal of the operational amplifier 104), the control signal SEL2 is set to a low level, and thus, the transistor 118 and the transistor 122 are turned off. Since the transistor 118 and the transistor 122 are transistors with significantly small off-state current, the voltage in the node B (reference voltage Vref) and voltage in the node C (reference voltage Vb) can be held for a long time.

Next, the control signal SEL1 is set to a low level and the transistor 115 is turned off. Thus, supply of the first power supply voltage V1 to the reference voltage generation circuit 101 from the first terminal is stopped. Since the first power supply voltage V1 is not supplied to the reference voltage generation circuit 101, the reference voltage generation circuit 101 stops operating.

In the signal processing circuit illustrated in FIG. 5, the transistor 122 with significantly small off-state current is used in the holding circuit 108. Therefore, by turning off the transistor 122, the voltage in the node C (reference voltage Vb) can be held for a long time. Thus, even when the reference voltage generation circuit 101 stops operating, the reference voltage Vb can still be supplied to the transistor 121. Similarly, the transistor 118 with significantly small off-state current is used in the holding circuit 107. Therefore, by turning off the transistor 118, the voltage in the node B (reference voltage Vref) can be held for a long time. Thus, even when the reference voltage generation circuit 101 stops operating, the reference voltage Vref can still be supplied to the non-inverting input terminal of the operational amplifier 104.

According to an embodiment of the present invention, since the transistor 122 including an oxide semiconductor is used as the switch 119, the off-state current thereof can be 100 yA. When the capacitance of the capacitor 120 is, for example, 1 pF, the node C can hold the reference voltage Vb for 10⁷ seconds (approximately 115 days).

Similarly, since the transistor 118 including an oxide semiconductor is used as the switch 113, the off-state current thereof can be 100 yA. When the capacitance of the capacitor 114 is, for example, 1 pF, the node B can hold the reference voltage Vref for 10⁷ seconds (approximately 115 days).

Accordingly, the reference voltage generation circuit 101 can stop operating for 10⁷ seconds (approximately 115 days). Before 10⁷ seconds (approximately 115 days) pass, the reference voltage generation circuit 101 may operate and the reference voltage Vb and the reference voltage Vref may be output to the holding circuit 108 and the holding circuit 107, respectively, by turning on the transistor 115 and supplying the first power supply voltage V1 to the reference voltage generation circuit 101.

In an embodiment of the present invention, transistors each of whose channels is formed in an oxide semiconductor film are used as the switches 113 and 119. For example, even when the switch 113 is turned off after a potential of the node B at which the switch 113 and the capacitor 114 are connected is kept constant, the amount of electric charges leaking through the switch 113 can be extremely small.

Therefore, when the switch 119 included in the holding circuit 108 is in an off state, the voltage output from the reference voltage generation circuit 101 can be held in the node C at which the switch 119 and the capacitor 120 are connected. Further, when the switch 113 included in the holding circuit 107 is in an off state, the voltage output from the voltage divider circuit 102 can be held in the node B at which the switch 113 and the capacitor 114 are connected.

Accordingly, the reference voltage generation circuit 101 does not need to keep outputting voltage to the bias circuit 109 or the operational amplifier 104, so that the reference voltage generation circuit 101 does not need to continuously operate. Thus, supply of power to the reference voltage generation circuit 101 can be stopped by turning off the transistor 115, whereby power consumed by the reference voltage generation circuit 101 can be reduced.

In this embodiment, although the case where the switch 113 and the switch 119 are each a transistor including an oxide semiconductor is described, the switch 103 may be a transistor including an oxide semiconductor.

Further, the switch 103, the switch 113, and the switch 119 may each be a transistor in which upper and lower gates are provided with an oxide semiconductor layer provided therebetween. In the case of the switch 103, the control signal SEL1 can be input to one gate, and a different control signal can be input to the other gate. In the case of the switch 113 and the switch 119, the control signal SEL2 can be input to one gate and a different control signal can be input to the other gate. The different control signal may be a signal with a fixed potential. The fixed potential may be either a low power supply potential or a high power supply potential. Note that the upper and lower gates may be electrically connected to each other and a control signal may be input. The threshold voltage of the transistor or the like can be controlled by a signal input to the other gate. Further, the off-state current of the transistor can be further reduced.

Although the case where the control signal SEL1 and the control signal SEL2 are different signals is described in this embodiment, the control signal SEL1 and the control signal SEL2 may be the same signal.

In the case where the reference voltage generation circuit 101, the voltage divider circuit 102, and the operational amplifier 104 include transistors, the transistors may each be a transistor whose channel is formed in a layer or a substrate including a semiconductor other than an oxide semiconductor. For example, the transistors can each be a transistor whose channel is formed in a silicon layer or a silicon substrate.

FIG. 6 illustrates the signal processing circuit illustrated in FIG. 4 in more detail.

The reference voltage generation circuit 101 includes the transistors 131 to 134 and the resistor 135. The node b is connected to the gate of the transistor 136 in the voltage divider circuit 102 and one of a source and a drain of the transistor 122 in the holding circuit 108. The reference voltage Vb is the voltage in the node b.

The voltage divider circuit 102 includes the transistor 136 and the resistor 137. The one of the source and the drain of the transistor 136 is connected to the one of the source and the drain of the transistor 118 in the holding circuit 107.

The operational amplifier 104 includes the transistors 138 to 141, the transistor 143, and the capacitor 144. The transistor 138 and the transistor 139 form a differential circuit. The transistor 140 and the transistor 141 form a current mirror circuit. The transistor 143 and the capacitor 144 form a buffer circuit.

Although an example in which a signal processing circuit includes an operational amplifier is described in this embodiment, the signal processing circuit may include a comparator instead of the operational amplifier.

The bias circuit 109 includes the transistor 121 and a transistor 145. The transistor 121 and the transistor 145 are p-channel transistors.

In the signal processing circuit illustrated in FIG. 4, FIG. 5, and FIG. 6, the holding circuit 108 is connected between the reference voltage generation circuit 101 and the bias circuit 109, so that the reference voltage Vb output from the reference voltage generation circuit 101 can be held in the holding circuit 108. Further, the holding circuit 107 is connected between the voltage divider circuit 102 and the operational amplifier 104, so that the reference voltage Vref output from the voltage divider circuit 102 can be held in the holding circuit 107. Thus, the reference voltage generation circuit 101 can stop operating during a period in which the reference voltage Vb is held in the holding circuit 108 and the reference voltage Vref is held in the holding circuit 107, so that power consumed by the reference voltage generation circuit 101 can be reduced. Consequently, power consumed by the signal processing circuit can be reduced.

Next, another embodiment of a signal processing circuit according to an embodiment of the present invention will be described with reference to FIG. 7 and FIG. 8.

FIG. 7 is a block diagram of a signal processing circuit. The signal processing circuit illustrated in FIG. 7 includes the reference voltage generation circuit 101, the voltage divider circuit 102, the switch 103, the operational amplifier 104, the bias circuit 105, the holding circuit 106, the holding circuit 107, the holding circuit 108, and the bias circuit 109.

The reference voltage generation circuit 101 is connected between the first terminal supplied with the first power supply voltage V1 and the second terminal supplied with the second power supply voltage V2, and outputs the reference voltage Va to the bias circuit 105 and the reference voltage Vb to the voltage divider circuit 102 and the holding circuit 108. The first power supply voltage V1 is VDD and the second power supply voltage V2 is GND, for example.

The voltage divider circuit 102 is connected between the first terminal and the second terminal, and divides the reference voltage Vb to output the reference voltage Vref to the non-inverting input terminal of the operational amplifier 104.

The switch 103 is connected between the first terminal and the reference voltage generation circuit 101, and is turned on or off in accordance with the control signal SEL1. In the case where the switch 103 is in an on state, the first power supply voltage V1 is supplied to the reference voltage generation circuit 101 from the first terminal. In the case where the switch 103 is in an off state, supply of the first power supply voltage V1 to the reference voltage generation circuit 101 from the first terminal is stopped.

In the operational amplifier 104, the reference voltage Vref is input to the non-inverting input terminal and the output voltage Vout is output from the output terminal. Further, part of the output voltage Vout is fed back to the inverting input terminal.

The bias circuit 109 is connected between the first terminal and the operational amplifier 104. The bias circuit 105 is connected between the second terminal and the operational amplifier 104. The bias circuit 109 and the bias circuit 105 each supply bias current to the operational amplifier 104.

As in the signal processing circuit illustrated in FIG. 1, the holding circuit 106 is connected between the reference voltage generation circuit 101 and the bias circuit 105, and the holding circuit 107 is connected between the voltage divider circuit 102 and the non-inverting input terminal of the operational amplifier 104. As in the signal processing circuit illustrated in FIG. 4, the holding circuit 108 is connected between the reference voltage generation circuit 101 and the bias circuit 109.

Each of the holding circuits 106 to 108 includes a switch and a capacitor. The switches included in the holding circuits 106 to 108 are turned on or off in accordance with the control signal SEL2.

FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, and FIG. 7 can be referred to for the details of the holding circuits 106 to 108.

FIG. 8 illustrates examples of the operational amplifier 104, the bias circuit 105, and the bias circuit 109 in the signal processing circuit illustrated in FIG. 7.

The operational amplifier 104 includes transistors 151 to 162, a resistor 163, and a capacitor 164. The transistors 151 to 156 are p-channel transistors and the transistors 157 to 162 are n-channel transistors.

A bias circuit 105 a includes a transistor 165 and a bias circuit 105 b includes a transistor 166 and a transistor 167. The transistors 165 to 167 are n-channel transistors.

The bias circuit 109 includes a transistor 168 and a transistor 169. The transistor 168 and the transistor 169 are p-channel transistors.

A terminal A corresponds to the node A of the holding circuit 106 in the signal processing circuit illustrated in FIG. 7, a terminal B corresponds to the node B of the holding circuit 107 in the signal processing circuit illustrated in FIG. 7, and a terminal C corresponds to the node C of the holding circuit 108 in the signal processing circuit illustrated in FIG. 7.

In the signal processing circuit illustrated in FIG. 7 and FIG. 8, the holding circuit 106 is connected between the reference voltage generation circuit 101 and the bias circuit 105 a, so that the reference voltage Va output from the reference voltage generation circuit 101 can be held in the holding circuit 106. The holding circuit 107 is connected between the voltage divider circuit 102 and the operational amplifier 104, so that the reference voltage Vref output from the voltage divider circuit 102 can be held in the holding circuit 107. The holding circuit 108 is connected between the reference voltage generation circuit 101 and the bias circuit 109, so that the reference voltage Vb output from the reference voltage generation circuit 101 can be held in the holding circuit 108.

Thus, the reference voltage generation circuit 101 can stop operating during a period in which the reference voltage Va is held in the holding circuit 106, the reference voltage Vref is held in the holding circuit 107, and the reference voltage Vb is held in the holding circuit 108, so that power consumed by the reference voltage generation circuit 101 can be reduced. Consequently, power consumed by the signal processing circuit can be reduced.

The signal processing circuit described in this embodiment can be used for, for example, an AC-DC converter, a sensor, or the like. The signal processing circuit described in this embodiment is particularly effectively used in a circuit in which an analog circuit such as an operational amplifier or a comparator is used and a fixed voltage or a signal is continuously output.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 3

In this embodiment, another embodiment of a signal processing circuit according to an embodiment of the present invention will be described with reference to FIG. 11.

FIG. 11 is a circuit diagram of a signal processing circuit. The signal processing circuit illustrated in FIG. 11 includes a reference voltage generation circuit 190, the operational amplifier 104, the holding circuit 107, a holding circuit 171, a transistor 172, and resistors 173 and 174.

In this embodiment, the structure of the reference voltage generation circuit 190 illustrated in FIG. 11 is partly different from the structure of the reference voltage generation circuit 101 described in the above embodiments. The reference voltage generation circuit 190 illustrated in FIG. 11 includes a holding circuit 175, a switch 176, a resistor 177, and transistors 178 and 179. The holding circuit 175 includes a switch 180 and a capacitor 181. The reference voltage generation circuit 190 is connected between the first terminal supplied with the first power supply voltage V1 and the second terminal supplied with the second power supply voltage V2, and outputs the reference voltage Vref to the holding circuit 107.

The switch 176 is connected between the first terminal and one terminal of the resistor 177 and is turned on or off in accordance with a control signal SEL3. In the case where the switch 176 is in an on state, the first power supply voltage V1 is supplied to the reference voltage generation circuit 190 from the first terminal. In the case where the switch 176 is in an off state, supply of the first power supply voltage V1 to the reference voltage generation circuit 190 from the first terminal is stopped.

The other terminal of the resistor 177 is electrically connected to a gate and one of a source and a drain of the transistor 178 and one end of the switch 180. The other end of the switch 180 is electrically connected to one of a pair of electrodes of the capacitor 181 and a gate of the transistor 179. One of a source and a drain of the transistor 179 is electrically connected to the first terminal. The other of the source and the drain of the transistor 178, the other of the pair of electrodes of the capacitor 181, and the other of the source and the drain of the transistor 179 are electrically connected to the second terminal.

The holding circuit 175 includes the switch 180 and the capacitor 181. The switch 180 in the holding circuit 175 is, for example, a transistor which is turned on or off in accordance with a control signal SEL4. A transistor with significantly small off-state current is used as the transistor.

When a transistor with extremely small off-state current is used as the switch 180 in the holding circuit 175 and the transistor is in an off state, voltage of the one of the pair of electrodes of the capacitor 181 can be held for a long time. In other words, in the case where the switch 180 is in an off state, the reference voltage Vref can be held in the holding circuit 175 for a long time.

The reference voltage Vref is input to the inverting input terminal of the operational amplifier 104. The non-inverting input terminal of the operational amplifier 104 is connected to the holding circuit 171. The output terminal of the operational amplifier 104 is connected to a gate of the transistor 172.

One of a source and a drain of the transistor 172 is connected to the first terminal and the other is connected to one terminal of the resistor 173 and the output Terminal. The output voltage Vout is output from the output terminal. The other terminal of the resistor 173 is connected to one terminal of the resistor 174. The other terminal of the resistor 174 is connected to the second terminal.

The holding circuit 171 includes a switch 182 and a capacitor 183. The switch 182 in the holding circuit 171 is, for example, a transistor which is turned on or off in accordance with a control signal SEL5. A transistor with significantly small off-state current is used as the transistor.

When a transistor with extremely small off-state current is used as the switch 182 in the holding circuit 171 and the transistor is in an off state, voltage of one of a pair of electrodes of the capacitor 183 can be held for a long time. In other words, in the case where the switch 182 is in an off state, voltage of a node D can be held in the holding circuit 171 for a long time.

Next, operation of the signal processing circuit illustrated in FIG. 11 is described.

First, the control signal SEL3 is input to the switch 176 and the switch 176 is turned on, whereby the first power supply voltage V1 is supplied to the reference voltage generation circuit 190 from the first terminal. In the case where the switch 176 is an n-channel transistor, a high-level potential may be input as the control signal SEL3, whereas in the case where the switch 176 is a p-channel transistor, a low-level potential may be input as the control signal SEL3. Note that described below is the case where the switch 113, the switch 182, the switch 176, and the switch 180 are n-channel transistors. In this case, the control signal SEL4 is set to a high level and the switch 180 is turned on, so that the reference voltage Vref is output to the holding circuit 107.

The control signal SEL2 is set to a high level and the switch 113 is turned on, so that the reference voltage Vref output from the reference voltage generation circuit 190 is output to the inverting input terminal of the operational amplifier 104. Consequently, the operational amplifier 104 operates, and voltage output from the output terminal of the operational amplifier 104 is input to the gate of the transistor 172.

After the signal processing circuit illustrated in FIG. 11 reaches a steady state (the state where the reference voltage Vref is normally supplied to the inverting input terminal of the operational amplifier), the control signal SEL4 is set to a low level, so that the switch 180 is turned off. A transistor with significantly small off-state current is used as the switch 180, whereby the reference voltage Vref can be held for a long time.

Since the reference voltage Vref can be held for a long time, the first power supply voltage V1 does not need to be continuously supplied to the reference voltage generation circuit 190 from the first terminal. Therefore, the switch 176 can be turned off by setting the control signal SEL3 to a low level.

Further, in the signal processing circuit illustrated in FIG. 11, in order that a potential of an output (VOUT) node is kept constant even when load change occurs on the VOUT side, a feedback portion is provided for the operational amplifier 104 for feedback control in some cases. However, the operational amplifier 104 constantly consumes power; therefore, the switch 182 in the holding circuit 171 is turned off so as to fix the voltage of a feedback input portion in the case where feedback is not needed (e.g., in the case where load change on the output side is small). Further, in the case where the switch 182 in the holding circuit 171 is turned off, the switch 113 in the holding circuit 107 needs to be turned off. Thus, power consumption of the operational amplifier 104 can be further reduced in the case where feedback is not needed.

Although a voltage divider circuit is not provided in the signal processing circuit in this embodiment, a voltage divider circuit may be provided as in the signal processing circuits described in the above embodiments. For example, in FIG. 11, a voltage divider circuit may be connected between the first terminal and the second terminal and the reference voltage Vref of the reference voltage generation circuit 190 may be input to the voltage divider circuit. In this case, output of the voltage divider circuit may be input to the holding circuit 107 and the output terminal of the operational amplifier 104.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 4

In this embodiment, an example of a power supply control device in which any of the signal processing circuits described in the above embodiments can be used will be described with reference to FIG. 9. A power supply control device 300 illustrated in FIG. 9 supplies power to external devices by outputting AC signals which are input from a terminal AC_IN and a terminal AC_INB, from a terminal AC_OUT and a terminal AC_OUTB.

The power supply control device 300 includes a main switch 301, a sub-switch 302, and a data processing device 303. The power supply control device 300 further includes a rectifier circuit 304, an AC/DC converter 305, a DC/DC converter 306, a capacitor 307, and a nonvolatile memory 308. The data processing device 303 includes a volatile memory unit 309, a nonvolatile memory unit 310, and a sensor 311.

The main switch 301 is turned on, whereby the AC signals which are input from the terminal AC_IN and the terminal AC_INB are output from the terminal AC_OUT and the terminal AC_OUTB to the external devices. The main switch 301 is turned off, whereby the output of the AC signals which are input from the terminal AC_IN and the terminal AC_INB, from the terminal AC_OUT and the terminal AC_OUTB to the external devices is stopped. The main switch 301 is turned on or off by being controlled by the data processing device 303 in accordance with a status of use of the external devices. Turning off the main switch 301 makes it possible to reduce the standby power of the external devices.

The sub-switch 302 is turned on, whereby the AC signals which are input from the terminal AC_IN and the terminal AC_INB are output to the rectifier circuit 304. The sub-switch 302 is turned off, whereby the output of the AC signals which are input from the terminal AC_IN and the terminal AC_NB, to the rectifier circuit 304 is stopped. The sub-switch 302 is turned on or off by being controlled by the data processing device 303.

As the main switch and the sub-switch which are described in this specification, a switch which is capable of mechanically operating, such as a relay circuit, or a switch which is capable of electrical operation, such as a thyristor or a power transistor, can be used.

The rectifier circuit 304 is a circuit for rectifying an AC signal which is input.

The AC/DC converter 305 is a circuit for smoothing a signal which includes a ripple rectified in the rectifier circuit 304 into a DC signal to adjust a power factor.

The DC/DC converter 306 is a circuit for converting the DC signal obtained by the conversion in the AC/DC converter 305 into a DC signal having a voltage at which the data processing device 303 can operate.

The capacitor 307 is provided to hold the voltage which is obtained in the DC/DC converter 306 and at which the data processing device 303 can operate.

The nonvolatile memory 308 is a circuit for storing data or a program to be processed in the data processing device 303. Note that examples of a memory element included in the nonvolatile memory 308 include a ferroelectric memory (FeRAM), a magnetic memory (MRAM), a phase-change memory (PRAM), and a resistive random access memory (ReRAM) which utilizes an electric-field induced giant resistance change, in addition to a flash memory. The memory element may be any memory element as long as it can hold data even when not powered.

The volatile memory unit 309 included in the data processing device 303 is a memory circuit which stores a result of arithmetic performed in the data processing device 303, or data or a program which is used for the arithmetic when power is supplied. The memory circuit corresponds to a register which has a function of temporarily storing data in the data processing device 303. For example, the volatile memory unit 309 can be formed using a flip-flop. The volatile memory unit 309 is preferably configured to store data at a higher speed than the nonvolatile memory unit 310. When the volatile memory unit 309 stores data at a high speed, the performance of the data processing device 303 can be improved.

The nonvolatile memory unit 310 included in the data processing device 303 is a circuit for storing the result of the arithmetic or the data or the program used for the arithmetic, which is stored in the data processing device 303 when the supply of power is not performed. For example, the nonvolatile memory unit 310 can be formed using a nonvolatile memory element.

The data processing device 303 controls an on state and an off state of the main switch 301, controls an on state and an off state of the sub-switch 302, and performs arithmetic processing which is necessary for operating the devices provided in the power supply control device 300.

For example, the data processing device 303 makes data in process saved from the volatile memory unit 309 to the nonvolatile memory unit 310 every certain period and turns off the sub-switch 302. In addition, the data processing device 303 operates to turn on the sub-switch 302, return the data that is saved in the nonvolatile memory unit 310 to the volatile memory unit 309, and perform arithmetic processing again.

Further, the data processing device 303 includes the sensor 311. With the sensor 311, arithmetic processing can be performed in accordance with a signal from the sensor 311 and an on state and an off state of the main switch 301 can be controlled if needed.

Any of the signal processing circuits described in the above embodiments can be used as the sensor 311 included in the data processing device. By using any of the signal processing circuits described in the above embodiments as the sensor 311, the reference voltage output from the reference voltage generation circuit can be held in the holding circuit in the signal processing circuit. Accordingly, the reference voltage generation circuit can stop operating during a period in which the reference voltage is held in the holding circuit. Thus, power consumption of the reference voltage generation circuit can be reduced, leading to a reduction in power consumption of the signal processing circuit. Further, power consumption of the power supply control device including the signal processing circuit can be reduced.

Embodiment 5

In this embodiment, an example of a cross-sectional structure of a signal processing circuit according to an embodiment of the present invention will be described with reference to FIG. 10.

In the signal processing circuits described in the above embodiment, the reference voltage generation circuit 101, the voltage divider circuit 102, and the operational amplifier 104 are each formed using a transistor including silicon or the like, and the holding circuit 106, the holding circuit 107, the holding circuit 108, and the like stacked over those circuits are each formed using a transistor including an oxide semiconductor.

FIG. 10 illustrates a cross section of part of a signal processing circuit according to an embodiment of the present invention. The signal processing circuit illustrated in FIG. 10 includes an n-channel transistor and a p-channel transistor each including a first semiconductor material (e.g., silicon) in a lower portion and a transistor including a second semiconductor material (e.g., an oxide semiconductor) and a capacitor in an upper portion.

<Structure of Transistor in Lower Portion>

An n-channel transistor 510 includes a channel formation region 501 provided in a substrate 500 including a semiconductor material, low-concentration impurity regions 502 and high-concentration impurity regions 503 (collectively simply referred to as impurity regions in some cases) with the channel formation region 501 provided between the impurity regions, intermetallic compound regions 507 provided in contact with the impurity regions, a gate insulating film 504 a provided over the channel formation region 501, a gate electrode layer 505 a provided over the gate insulating film 504 a, and a source electrode layer 506 a and a drain electrode layer 506 b provided in contact with the intermetallic compound regions 507. Sidewall insulating films 508 a are provided on side surfaces of the gate electrode layer 505 a. An interlayer insulating film 521 and an interlayer insulating film 522 are provided to cover the transistor 510. The source electrode layer 506 a and the drain electrode layer 506 b are connected to the intermetallic compound regions 507 through openings formed in the interlayer insulating film 521 and the interlayer insulating film 522.

A p-channel transistor 520 includes a channel formation region 511 provided in the substrate 500 including the semiconductor material, low-concentration impurity regions 512 and high-concentration impurity regions 513 (collectively simply referred to as impurity regions in some cases) with the channel formation region 511 provided between the impurity regions, intermetallic compound regions 517 provided in contact with the impurity regions, a gate insulating film 504 b provided over the channel formation region 511, a gate electrode layer 505 b provided over the gate insulating film 504 b, and a source electrode layer 506 c and a drain electrode layer 506 d provided in contact with the intermetallic compound regions 517. Sidewall insulating films 508 b are provided on side surfaces of the gate electrode layer 505 b. The interlayer insulating film 521 and the interlayer insulating film 522 are provided to cover the transistor 520. The source electrode layer 506 c and the drain electrode layer 506 d are connected to the intermetallic compound regions 517 through openings formed in the interlayer insulating film 521 and the interlayer insulating film 522.

Further, element separation insulating films 509 are provided for the substrate 500 to surround each of the transistor 510 and the transistor 520.

Although the case where the channels of the transistors 510 and 520 are formed in the semiconductor substrate is illustrated in FIG. 10, the channels of the transistors 510 and 520 may be formed in an amorphous semiconductor film or a polycrystalline semiconductor film formed over an insulating surface. Alternatively, the channels may be formed in a single crystal semiconductor film, like the case of using an SOI substrate.

When the transistors 510 and 520 are formed using a single crystal semiconductor substrate as the semiconductor substrate, the transistors 510 and 520 can operate at high speed. Accordingly, it is preferable that the reference voltage generation circuit, the voltage divider circuit, the operational amplifier, and the like in any of the signal processing circuits described in the above embodiments be formed using a single crystal semiconductor substrate.

The transistor 510 and the transistor 520 are connected to each other through a wiring 523, and an insulating film 524 is provided over the wiring 523. Further, conductive layers 525 a and 525 b and an insulating film 526 are provided over the insulating film 524. The insulating film 526 is preferably formed in such a manner that after the conductive layers 525 a and 525 b are formed over the insulating film 524, an insulating film is formed over the conductive layers 525 a and 525 b and then the insulating film is subjected to polishing treatment until upper surfaces of the conductive layers 525 a and 525 b are exposed.

<Structure of Transistor in Upper Portion>

A transistor 530 in an upper portion is a transistor whose channel is formed in a film of a semiconductor having a wider band gap than silicon. The transistor 530 includes the conductive layer 525 b provided over the insulating film 524, an insulating film 531 and an insulating film 532 provided over the conductive layer 525 b, a semiconductor film 533 provided over the insulating film 532, a source electrode layer 534 a and a drain electrode layer 534 b provided in contact with the semiconductor film 533, a gate insulating film 535 provided over the semiconductor film 533, the source electrode layer 534 a, and the drain electrode layer 534 b, and a gate electrode layer 536 a provided over the gate insulating film 535. Note that the conductive layer 525 b serves as a gate electrode layer.

FIG. 10 illustrates the case where upper and lower gate electrode layers are provided with a semiconductor film provided therebetween. A signal for controlling an on state and an off state is supplied to one of the gate electrode layers and the other of the gate electrode layers may be in a floating state (i.e., electrically insulated) or in a state where a potential is supplied. In the latter case, potentials with the same level may be supplied to the pair of gate electrode layers, or a fixed potential such as a ground potential may be supplied only to the other of the gate electrode layers. By controlling the level of a potential supplied to the other of the gate electrode layers, the threshold voltage of the transistor can be controlled.

A conductive layer 534 c is provided over the insulating film 532, the gate insulating film 535 is provided over the conductive layer 534 c, and a conductive layer 536 b is provided over the gate insulating film 535. The conductive layer 534 c, the gate insulating film 535, and the conductive layer 536 b form a capacitor 540.

Further, an interlayer insulating film 537 and an interlayer insulating film 538 are provided to cover the transistor 530 and the capacitor 540. The source electrode layer 534 a is connected to a wiring 539 through an opening formed in the interlayer insulating film 537 and the interlayer insulating film 538.

As the film of the semiconductor having a wider band gap than silicon, a film of a compound semiconductor such as an oxide semiconductor or a nitride semiconductor can be given. This embodiment explains the case where an oxide semiconductor is used for the semiconductor film 533.

The oxide semiconductor used for the transistor 530 is preferably a purified oxide semiconductor in which impurities serving as electron donors (donors), such as moisture or hydrogen, are reduced and oxygen vacancies are reduced. The purified oxide semiconductor is an i-type (intrinsic) semiconductor or a substantially i-type semiconductor. Therefore, a transistor including the oxide semiconductor has a characteristic of significantly small off-state current. Furthermore, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. With the use of the oxide semiconductor film which is purified by sufficiently reducing the concentration of impurities such as moisture or hydrogen and by reducing oxygen vacancies, the off-state current of the transistor can be significantly reduced.

Specifically, various experiments can prove small off-state current of a transistor in which a purified oxide semiconductor is used for a semiconductor film. For example, even in an element with a channel width of 1×10⁶ μm and a channel length of 10 μm, in a range from 1 V to 10 V of voltage (drain voltage) between a source terminal and a drain terminal, off-state current can be smaller than or equal to the measurement limit of a semiconductor parameter analyzer, that is, smaller than or equal to 1×10⁻¹³ A. In this case, it can be found that an off-state current density corresponding to a value obtained by dividing the off-state current by the channel width of the transistor is less than or equal to 100 zA/μm. In addition, a capacitor and a transistor were connected to each other and an off-state current density was measured by using a circuit in which electric charge flowing into or from the capacitor was controlled by the transistor. In the measurement, the purified oxide semiconductor film was used for a channel formation region in the transistor, and the off-state current density of the transistor was measured from change in the amount of electric charge of the capacitor per unit time. As a result, it is found that, in the case where the voltage between the source terminal and the drain terminal of the transistor is 3 V, a smaller off-state current density of several tens of yoctoamperes per micrometer (yA/μm) can be obtained. Consequently, it can be said that a transistor whose channel formation region is formed in a purified oxide semiconductor film has much smaller off-state current than a transistor including silicon.

The oxide semiconductor preferably includes at least indium (In) or zinc (Zn). As a stabilizer for reducing variation in electric characteristics of a transistor including the oxide semiconductor, it is preferable that one or more selected from gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr) be contained.

As another stabilizer, one or plural kinds of lanthanoid such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) may be contained.

As the oxide semiconductor, for example, it is possible to use indium oxide, tin oxide, zinc oxide, a two-component metal oxide such as an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, or an In—Ga-based oxide, a three-component metal oxide such as an In—Ga—Zn-based oxide (also referred to as IGZO), an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Hf—Zn-based oxide, an In—La—Zn-based oxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, or an In—Lu—Zn-based oxide, or a four-component metal oxide such as an In—Sn—Ga—Zn-based oxide, an In—Hf—Ga—Zn-based oxide, an In—Al—Ga—Zn-based oxide, an In—Sn—Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, or an In—Hf—Al—Zn-based oxide.

Note that, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn, and there is no limitation on the ratio of In, Ga, and Zn. In addition, the In—Ga—Zn-based oxide may contain a metal element other than In, Ga, and Zn. The In—Ga—Zn-based oxide has sufficiently high resistance when no electric field is applied thereto, so that off-state current can be sufficiently reduced. Further, the In—Ga—Zn-based oxide has high mobility.

For example, an In—Ga—Zn-based oxide with an atomic ratio of In:Ga:Zn=1:1:1 (=⅓:⅓:⅓) or In:Ga:Zn=2:2:1 (=⅖:⅖:⅕), or an oxide with an atomic ratio close to the above atomic ratios can be used. Alternatively, an In—Sn—Zn-based oxide with an atomic ratio of In:Sn:Zn=1:1:1 (=⅓:⅓:⅓), In:Sn:Zn=2:1:3 (=⅓:⅙:½), or In:Sn:Zn=2:1:5 (=¼:⅛:⅝), or an oxide with an atomic ratio close to the above atomic ratios may be used.

For example, with an In—Sn—Zn-based oxide, high mobility can be realized relatively easily. However, even with an In—Ga—Zn-based oxide, mobility can be increased by reducing the defect density in the bulk.

An oxide semiconductor film may be in a non-single-crystal state, for example. The non-single-crystal state is, for example, structured by at least one of c-axis aligned crystal (CAAC), polycrystal, microcrystal, and an amorphous part. The density of defect states of an amorphous part is higher than those of microcrystal and CAAC. The density of defect states of microcrystal is higher than that of CAAC. Note that an oxide semiconductor including CAAC is referred to as a CAAC-OS (c-axis aligned crystalline oxide semiconductor).

For example, an oxide semiconductor film may include a CAAC-OS. In the CAAC-OS, for example, c-axes are aligned, and a-axes and/or b-axes are not macroscopically aligned.

For example, an oxide semiconductor film may include microcrystal. Note that an oxide semiconductor including microcrystal is referred to as a microcrystalline oxide semiconductor. A microcrystalline oxide semiconductor film includes microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example.

For example, an oxide semiconductor film may include an amorphous part. Note that an oxide semiconductor including an amorphous part is referred to as an amorphous oxide semiconductor. An amorphous oxide semiconductor film, for example, has disordered atomic arrangement and no crystalline component. Alternatively, an amorphous oxide semiconductor film is, for example, absolutely amorphous and has no crystal part.

Note that an oxide semiconductor film may be a mixed film including any of a CAAC-OS, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. The mixed film, for example, includes a region of an amorphous oxide semiconductor, a region of a microcrystalline oxide semiconductor, and a region of a CAAC-OS. Further, the mixed film may have a stacked structure including a region of an amorphous oxide semiconductor, a region of a microcrystalline oxide semiconductor, and a region of a CAAC-OS, for example.

Note that an oxide semiconductor film may be in a single-crystal state, for example.

An oxide semiconductor film preferably includes a plurality of crystal parts. In each of the crystal parts, a c-axis is preferably aligned in a direction parallel to a normal vector of a surface where the oxide semiconductor film is formed or a normal vector of a surface of the oxide semiconductor film. Note that, among crystal parts, the directions of the a-axis and the b-axis of one crystal part may be different from those of another crystal part. An example of such an oxide semiconductor film is a CAAC-OS film.

Note that in most cases, a crystal part in the CAAC-OS film fits inside a cube whose one side is less than 100 nm. In an image obtained with a transmission electron microscope (TEM), a boundary between crystal parts in the CAAC-OS film are not clearly detected. Further, with the TEM, a grain boundary in the CAAC-OS film is not clearly found. Thus, in the CAAC-OS film, a reduction in electron mobility due to the grain boundary is suppressed.

In each of the crystal parts included in the CAAC-OS film, for example, a c-axis is aligned in a direction parallel to a normal vector of a surface where the CAAC-OS film is formed or a normal vector of a surface of the CAAC-OS film. Further, in each of the crystal parts, metal atoms are arranged in a triangular or hexagonal configuration when seen from the direction perpendicular to the a-b plane, and metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis. Note that, among crystal parts, the directions of the a-axis and the b-axis of one crystal part may be different from those of another crystal part. In this specification, a term “perpendicular” includes a range from 80° to 100°, preferably from 85° to 95°. In addition, a term “parallel” includes a range from −10° to 10°, preferably from −5° to 5°.

In the CAAC-OS film, distribution of crystal parts is not necessarily uniform. For example, in the formation process of the CAAC-OS film, in the case where crystal growth occurs from a surface side of the oxide semiconductor film, the proportion of crystal parts in the vicinity of the surface of the oxide semiconductor film is higher than that in the vicinity of the surface where the oxide semiconductor film is formed in some cases. Further, when an impurity is added to the CAAC-OS film, crystallinity of the crystal part in a region to which the impurity is added is lowered in some cases.

Since the c-axes of the crystal parts included in the CAAC-OS film are aligned in the direction parallel to a normal vector of a surface where the CAAC-OS film is formed or a normal vector of a surface of the CAAC-OS film, the directions of the c-axes may be different from each other depending on the shape of the CAAC-OS film (the cross-sectional shape of the surface where the CAAC-OS film is formed or the cross-sectional shape of the surface of the CAAC-OS film). Note that the film deposition is accompanied with the formation of the crystal parts or followed by the formation of the crystal parts through crystallization treatment such as heat treatment. Hence, the c-axes of the crystal parts are aligned in the direction parallel to a normal vector of the surface where the CAAC-OS film is formed or a normal vector of the surface of the CAAC-OS film.

In a transistor using the CAAC-OS film, change in electric characteristics due to irradiation with visible light or ultraviolet light is small. Thus, the transistor has high reliability.

In the case where the gate insulating films are formed using the same material, the amount of shift of the threshold voltage of the transistor can be controlled by the thickness ratio between the gate insulating films. When the thickness ratio of one of the gate insulating films to the other of the gate insulating films is 1:10, the amount of shift of the threshold voltage of the transistor tends to be high as compared to the case where the thickness ratio is 1:1.

It is preferable that hydrogen not be contained in the semiconductor film 533 before, during, and after the deposition. For example, it is preferable that hydrogen be contained as little as possible in the deposition of the semiconductor film 533 and that heat treatment for dehydration or dehydrogenation be performed after the deposition of the semiconductor film 533. Further, it is preferable that hydrogen be contained as little as possible in deposition of an insulating film in contact with the semiconductor film 533 and that heat treatment for dehydration or dehydrogenation be performed after the deposition of the insulating film.

When a film which prevents hydrogen from passing therethrough is used as the insulating film 531, hydrogen contained in the transistors in the lower portion, the insulating film 524, the interlayer insulating film 522, and the like can be prevented from reaching the semiconductor film 533. As the film which prevents hydrogen from passing therethrough, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like is preferably used. In addition, when a film which prevents hydrogen from passing therethrough is used as the interlayer insulating film 537, hydrogen contained in the interlayer insulating film 538 can be prevented from reaching the semiconductor film 533.

Treatment for supplying oxygen to the semiconductor film 533 is preferably performed in order to reduce oxygen vacancies contained in the semiconductor film 533. For example, when an insulating film containing an excess amount of oxygen is provided in contact with the semiconductor film 533 and heat treatment is performed, oxygen can be supplied to the semiconductor film 533 from the insulating film containing an excess amount of oxygen. Oxygen is supplied to the semiconductor film 533, whereby oxygen vacancies contained in the semiconductor film 533 can be reduced. Treatment for adding oxygen to the semiconductor film 533 may be performed after the semiconductor film 533 is subjected to dehydration or dehydrogenation treatment. As the treatment for adding oxygen, an oxygen radical, ozone, an oxygen atom, an oxygen ion, or the like is added to the semiconductor film 533 by an ion implantation method, an ion doping method, plasma treatment, or the like, for example.

When the amount of impurities and oxygen vacancies in the semiconductor film 533 is reduced in this manner, generation of carriers can be suppressed. Suppressing the increase in carrier density can suppress negative shift of the threshold voltage of the transistor due to the carrier density. As a result, the threshold voltage of the transistor can be easily controlled by a potential applied to the other of the gate electrodes of the transistor.

This embodiment can be combined with any of the other embodiments as appropriate.

This application is based on Japanese Patent Application serial no. 2012-090058 filed with Japan Patent Office on Apr. 11, 2012, the entire contents of which are hereby incorporated by reference. 

What is claimed is:
 1. A semiconductor device comprising: a first circuit electrically connected between a first terminal supplied with first power supply voltage and a second terminal supplied with second power supply voltage, the first circuit configured to output first reference voltage and second reference voltage; a second circuit electrically connected between the first terminal and the second terminal, the second circuit configured to divide the second reference voltage to output third reference voltage; a first switch electrically connected between the first terminal and the first circuit and turned on or off in accordance with a first signal; an operational amplifier whose non-inverting input terminal is supplied with the third reference voltage and whose inverting input terminal is supplied with output voltage; a third circuit configured to supply bias current to the operational amplifier; a fourth circuit electrically connected between the first circuit and the third circuit, the fourth circuit configured to hold the first reference voltage in accordance with a second signal; and a fifth circuit electrically connected between the second circuit and the non-inverting input terminal of the operational amplifier, the fifth circuit configured to hold the third reference voltage in accordance with the second signal, wherein the fourth circuit comprises a first transistor and a first capacitor, wherein the fifth circuit comprises a second transistor and a second capacitor, wherein one of a source and a drain of the first transistor is supplied with the first reference voltage, wherein the other of the source and the drain of the first transistor is electrically connected to the third circuit and the first capacitor, wherein one of a source and a drain of the second transistor is supplied with the third reference voltage, wherein the other of the source and the drain of the second transistor is electrically connected to the operational amplifier and the second capacitor, wherein each of the first transistor and the second transistor comprises an oxide semiconductor in a channel forming region, wherein the first circuit comprises a third transistor comprising silicon in a channel forming region, wherein the operational amplifier comprises a fourth transistor comprising silicon in a channel forming region, and wherein the first switch is turned off while the operational amplifier operates with the third reference voltage.
 2. The semiconductor device according to claim 1, wherein the third circuit is electrically connected between the operational amplifier and the second terminal.
 3. The semiconductor device according to claim 1, wherein the third circuit is electrically connected between the operational amplifier and the first terminal.
 4. The semiconductor device according to claim 1, wherein each of the first transistor and the second transistor is turned on or off in accordance with the second signal.
 5. The semiconductor device according to claim 1, further comprising a first insulating film over the third transistor and the fourth transistor, wherein the first transistor and the second transistor are provided over the first insulating film.
 6. The semiconductor device according to claim 1, wherein the first switch is a transistor comprising an oxide semiconductor in a channel forming region.
 7. A semiconductor device comprising: a first circuit electrically connected between a first terminal supplied with first power supply voltage and a second terminal supplied with second power supply voltage, the first circuit configured to output first reference voltage and second reference voltage; a first switch electrically connected between the first terminal and the first circuit and turned on or off in accordance with a first signal; a second circuit electrically connected between the first terminal and the second terminal, the second circuit configured to divide the second reference voltage to output third reference voltage; an operational amplifier whose non-inverting input terminal is supplied with the third reference voltage and whose inverting input terminal is supplied with output voltage; a third circuit electrically connected between the operational amplifier and the first terminal, the third circuit configured to supply bias current to the operational amplifier; a fourth circuit electrically connected between the operational amplifier and the second terminal, the fourth circuit configured to supply bias current to the operational amplifier; a fifth circuit electrically connected between the first circuit and the third circuit, the fifth circuit configured to hold the second reference voltage in accordance with a second signal; a sixth circuit electrically connected between the first circuit and the fourth circuit, the sixth circuit configured to hold the first reference voltage in accordance with the second signal; and a seventh circuit electrically connected between the second circuit and the non-inverting input terminal of the operational amplifier, the seventh circuit configured to hold the third reference voltage in accordance with the second signal, wherein the fifth circuit comprises a first transistor and a first capacitor, wherein the sixth circuit comprises a second transistor and a second capacitor, wherein the seventh circuit comprises a third transistor and a third capacitor, wherein one of a source and a drain of the first transistor is supplied with the second reference voltage, wherein the other of the source and the drain of the first transistor is electrically connected to the third circuit and the first capacitor, wherein one of a source and a drain of the second transistor is supplied with the first reference voltage, wherein the other of the source and the drain of the second transistor is electrically connected to the fourth circuit and the second capacitor, wherein one of a source and a drain of the third transistor is supplied with the third reference voltage, wherein the other of the source and the drain of the third transistor is electrically connected to the operational amplifier and the third capacitor, wherein each of the first transistor, the second transistor and the third transistor comprises an oxide semiconductor in a channel forming region, wherein the first circuit comprises a fourth transistor comprising silicon in a channel forming region, and wherein the operational amplifier comprises a fifth transistor comprising silicon in a channel forming region.
 8. The semiconductor device according to claim 7, wherein each of the first transistor, the second transistor and the third transistor is turned on or off in accordance with the second signal.
 9. The semiconductor device according to claim 7, further comprising a first insulating film over the fourth transistor and the fifth transistor, wherein the first transistor, the second transistor and the third transistor are provided over the first insulating film.
 10. The semiconductor device according to claim 7, wherein the first switch is a transistor comprising an oxide semiconductor in a channel forming region. 